DOI: 10.7763/IJCTE.2013.V5.805
Modeling and Simulating Network-on-Chip Designs: A Case Study of Fat Tree Interconnection Architecture
Abstract—In this paper we describe a fat-tree based Network-on-Chip (NOC) system that composed of processing nodes and communication switches. The IP node contains message generator and buffering. The switch uses wormhole technique which improved by virtual channel mechanism. The switch includes the following essential units: the router, input/output link controller units and arbitration unit. A discrete event simulator has been developed in C++ to analyze the proposed architecture. The obtained results clearly demonstrate both the efficiency and the applicability of fat tree structure to NOC design. In addition, VHDL code for the proposed algorithms has been prototyped in FPGA technology.
Index Terms—Network-on-chip, routing, switching, fat tree.
The authors are with the Computer Department, Faculty of Science, Tripoli University, Tripoli, Libya (e-mail: aziz239@yahoo.com, asma44441@yahoo.com).
Cite:Azeddien M. Sllame and Asma Alasar, "Modeling and Simulating Network-on-Chip Designs: A Case Study of Fat Tree Interconnection Architecture," International Journal of Computer Theory and Engineering vol. 5, no. 5, pp. 823-829, 2013.