doi: 10.7763/IJCTE.2013.V5.795
Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Array
Esraa Zeki Mohammed1
,
Haitham Kareem Ali2
- 1State Company for Internet Services, Ministry of Communcation, Kirkuk, Iraq.
- 2Communication Engineering Department, Sulaimani Technical College, Sulaimani, Iraq.
Abstract
In this paper a hardware implementation of an artificial neural network on Field Programmable Gate Arrays (FPGA) is presented. A digital system architecture is designed to realize a feed forward multilayer neural network. The designed architecture is described using Very High Speed Integrated Circuits Hardware Description Language (VHDL). The parallel structure of a neural network makes it potentially fast for the computation of certain tasks. The same feature makes a neural network well suited for implementation in VLSI technology. Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task.
Keywords
- Artificial neural network
- hardware description language
- field programmable gate arrays (FPGAs)
- sigmoid activation function
How to Cite
Esraa Zeki Mohammed and Haitham Kareem Ali, "Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Array," International Journal of Computer Theory and Engineering, vol. 5, no. 5, pp. 780-783, 2013. https://doi.org/10.7763/IJCTE.2013.V5.795
Copyright & License
Copyright © 2013 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).