doi: 10.7763/IJCTE.2019.V11.1240
Research on Digital Correlator Algorithm Based on FPGA
Guiling Sun
,
Jun Jia ,
Tianyu Geng ,
Xudong Ye
- College of Electronic Information and Optical Engineering, Nankai University, Tianjin, China.
Abstract
This paper designs and implements a parallel correlation algorithm for ultra-long sequence in large-scale field programmable gate array (FPGA). The operation speed is 64 times faster than traditional algorithms. Combining multiple data values in one RAM address improves the efficiency and avoids the time consumption caused by reading data repeatedly. The multi-group multiply accumulator is used to calculate the data read according to certain rules, which fully utilizes the advantages of parallel operation in FPGA and reduces the operation time. This algorithm overcomes the shortcomings of the limit of the number of multipliers in the serial pipeline operation method, which can only perform correlation operations on short sequences, and makes up that the general parallel algorithm is more convenient only for the correlation operation of the two signals without relative sliding, but the sequential control is too complex when the two signals have relative sliding.
Keywords
- Correlation operation
- FPGA
- parallel algorithm
How to Cite
Guiling Sun, Jun Jia, Tianyu Geng, and Xudong Ye, "Research on Digital Correlator Algorithm Based on FPGA," International Journal of Computer Theory and Engineering, vol. 11, no. 3, pp. 46-50, 2019. https://doi.org/10.7763/IJCTE.2019.V11.1240
Copyright & License
Copyright © 2019 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).