Abstract—An asynchronous circuit design methodology has been introduced as a novelty approach to future digital system design. Nevertheless, in order to implement the asynchronous circuit, there are various limitations. Especially, for the implementation on a commercialized field programmable gate array (FPGA), the vendors and design tools mainly support only synchronous circuit design. In this paper, we propose design techniques for implementing the asynchronous circuit on the commercial FPGA using the provided design tool. Then, with the proposed design techniques, we designed an asynchronous micro-controller based onaTIMSP430 instruction set architecture (ISA).We observe that the asynchronous core consumes lower power than the synchronous one. In addition, the asynchronous core also shows much more durability under conditions of unstable power supplies compared to the synchronous counterpart.
Index Terms—Asynchronous circuit, AFSM, bounded delay, FPGA.
Ziho Shin, Myeong-Hoon Oh, and Dongjae Kang are with Cloud Computing Research Group, Electronics and Telecommunication Research Institute (ETRI), Daejeon, Republic of Korea and Dept. of Computer S/W, University of Science and Technology (UST), Daejeon, Republic of Korea (e-mail: zshin@ ust.ac.kr , mhoonoh@etri.re.kr, djkang@etri.re.kr).
Hyukje Kwon and Hag Young Kim are with Cloud Computing Research Group, Electronics and Telecommunication Research Institute (ETRI), Daejeon, Republic of Korea (e-mail: heavenwing@etri.re.kr, h0kim@etri.re.kr).
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Cite:Ziho Shin, Myeong-Hoon Oh, Hyukje Kwon, Hagyoung Kim, and Dongjae Kang, "Implementation of an Asynchronous Micro-controlleron the Commercial FPGA," International Journal of Computer Theory and Engineering vol. 9, no. 6, pp. 466-472, 2017.
