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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2017 Vol.9(4): 250-255 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2017.V9.1146

Parallelizing the Coarsening Phase of Hyper-Edge Partitioning on the GPU Platform

Atefeh Taheri, Ali Jahanian, and Behin Molaie
Abstract—Abstract—Significant portion of digital design flow runtime is related to the physical design stages. Partitioning is a critical stage of physical design and its quality and runtime has considerable impact on physical design efficiency. In this paper, a new parallel partitioning algorithm is proposed and it is suitable for GPU system. In the proposed algorithm, coarsening phase of the partitioning is accelerated by parallelizing on GPU. Experimental results show that runtime can be improved up to 7x for attempted circuit with negligible quality degradation.

Index Terms—Index Terms—GPU programming, multilevel partitioning, parallel algorithms, physical design.

Atefe Taheri was with the Electronic and Computer Engineering Department, Shahid Beheshti University, Tehran, Iran (e-mail: atefetaheri1439@gmail.com). Ali Jahanian is with Electronic and Computer Engineering Department, Shahid Beheshti University, Tehran, Iran (e-mail: jahanian@sbu.ac.ir). Behin Molaie is with the Computer Engineering Department, Sharif University of Technology, Tehran, Iran (e-mail: molaie@ce.sharif.edu).

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Cite:Atefeh Taheri, Ali Jahanian, and Behin Molaie, "Parallelizing the Coarsening Phase of Hyper-Edge Partitioning on the GPU Platform," International Journal of Computer Theory and Engineering vol. 9, no. 4, pp. 250-255, 2017.

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