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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2020 Vol.12(3): 80-84 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2020.V12.1268

A Reconfigurable Model-Based Design for Rapid Prototyping on FPGA

Syed Jahanzeb Hussain Pirzada, Abid Murtaza, Tongge Xu, and Liu Jianwei
Abstract—The digital design methodologies are evolving with the increase of digital systems utilization in daily life. The Model Based Design (MBD) methodology provides a unique methodology for design and implementation of digital systems on Field Programmable Gate Array (FPGA). Recently, a lot of research effort has been put to exploit new methodologies for designing and prototyping of digital systems on FPGA. The FPGA hardware provides prototyping which provides means of verifying your design at an early stage of development cycle. This helps to evaluate design trade-offs by testing the design in real-time on hardware. Making prototypes is a common practice in research-oriented projects. However, it requires excess development time which increases time to market of the product. This paper illustrates the use of reconfigurable MBD for rapid prototyping of digital systems on Microsemi ACTEL FPGAs for improving the design-cycle and time-to-market of a product. The model is simulated to verify the functionality of the design at system-level and a high-level code is generated from the MBD toolset embedded in MATLAB for hardware implementation. Then, a High-Level Synthesis (HLS) is performed on the generated code which converts this high-level code into Verilog-HDL suitable for hardware implementation on FPGA. Hence, this work presents a methodology and its analysis for design of digital system using high-level synthesis on Microsemi ACTEL FPGA.

Index Terms—Model-based design, binary phase shift keying, high-level synthesis, field programmable gate array.

S. J. H. Pirzada, T. Xu, and L. Jianwei are with the School of Cyber Science and Technology, Beihang University, Beijing, China (e-mail: jahanzebp@ hotmail.com, xutg@buaa.edu.cn, liujianwei@buaa.edu.cn). A. Murtaza is with the School of Electronics and Information Engineering, Beihang University, Beijing, China (e-mail: abid_murtaza47@hotmail.com).

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Cite:Syed Jahanzeb Hussain Pirzada, Abid Murtaza, Tongge Xu, and Liu Jianwei, "A Reconfigurable Model-Based Design for Rapid Prototyping on FPGA," International Journal of Computer Theory and Engineering vol. 12, no. 3, pp. 80-84, 2020.

Copyright © 2020 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).


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