International Journal of Computer Theory and Engineering

Abstract

Multi-threading pipelined processor design enables high performance of a single processor core by exploiting both thread-level and instruction-level parallelism. However, when it is applied to embedded systems, its demanding for large register file, hence high resource overhead and energy consumption, becomes a big issue. In this paper, we propose a customization approach to reduce register file by maximally utilizing each of the registers used. The experiments on several applications demonstrate that with our approach, the register file for a single thread can be reduced by about 50%, based on which the multi-threading processor can achieve high performance while at low energy consumption - with 17-28% throughput improvement and 20% energy reduction when compared to the single-threading processor design.