Abstract—This paper proposes modified architecture of 21264, Out-Of-Order, six-way issue microprocessor. The proposed modified architecture implements Tomasulo’s algorithm using tournament branch prediction scheme to improve the performance of processor. Tomasulo's Algorithm controls the operation of the Common Data Bus (CDB) by means of tag mechanism. A tag is a 4-bit number used to identify separately each of eleven sources which can feed the CDB. The proposed modified architecture will evaluate branch outcome by taking both local and global history. The choice of global-versus-local branch prediction is made dynamically on a path-based predictor that decides which predictor to use, based on the past correctness of choice.
Index Terms—common data bus (CDB), tomasulo’s algorithm, tournament branch predictor.
Rubina Khanna is a post graduate student with DAVIET, Jalandhar, Punjab, India (firstname.lastname@example.org)
Vinay Chopra is Assistant Professor with DAVIET, Jalandhar, Punjab, India (email@example.com)
Sweta Verma is Associate Professor with GCET, Greater Noida, Uttar Pradesh, India. (firstname.lastname@example.org)
Cite: Rubina Khanna, Vinay Chopra, and Sweta Verma, "Modified Architectural Support to Implement Tomasulo’s Algorithm on Tournament Branch Predictor," International Journal of Computer Theory and Engineering vol. 3, no. 4, pp. 575-578, 2011.