doi: 10.7763/IJCTE.2011.V3.356
ASIC Implementation of Neural Network Based Image Compression
- 1College Gudur, Andhra Pradesh, India
- 2School of Advanced Studies Bangalore, Karnataka, India
Abstract
Image data consumes enormous bandwidth and storage space. Neural networks can be used for image compression. Neural network architectures have proven to be more reliable, robust, and programmable and offer better performance when compared with classical techniques. In this paper the main focus is development of new architectures for neural network based image compression optimizing area, power and speed as specific to ASIC implementation, and comparison with FPGA. The proposed architecture designs are realized on Spartan IIIE FPGA Using Xilinx ISE, and the ASIC implementation is carried out using Synopsys tools targeting 130nm TSMC Library. The ASIC implementation for 2 input and 16 input neuron with low power techniques adopted such as buffer insertion, clock gating etc,
Keywords
- Image compression
- neural networks
- FPGA
- ASIC
- CSD
How to Cite
K.Venkata Ramanaiah and Cyril Prasanna Raj, "ASIC Implementation of Neural Network Based Image Compression," International Journal of Computer Theory and Engineering, vol. 3, no. 4, pp. 494-498, 2011. https://doi.org/10.7763/IJCTE.2011.V3.356
Copyright & License
Copyright © 2011 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).