General Information
    • ISSN: 1793-8201 (Print), 2972-4511 (Online)
    • Abbreviated Title: Int. J. Comput. Theory Eng.
    • Frequency: Quarterly
    • DOI: 10.7763/IJCTE
    • Editor-in-Chief: Prof. Mehmet Sahinoglu
    • Associate Editor-in-Chief: Assoc. Prof. Alberto Arteta, Assoc. Prof. Engin Maşazade
    • Managing Editor: Ms. Mia Hu
    • Abstracting/Indexing: Scopus (Since 2022), INSPEC (IET), CNKI,  Google Scholar, EBSCO, etc.
    • Average Days from Submission to Acceptance: 192 days
    • APC: 800 USD
    • E-mail: editor@ijcte.org
    • Journal Metrics:
    • SCImago Journal & Country Rank
Article Metrics in Dimensions

IJCTE 2014 Vol.6(2): 160-169 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2014.V6.856

Efficient Design and Implementation of LTE Downlink Control Information Decoder

Mohamed S. Abo Zeid, Khaled M. Elsayed, Mohamed E. Nasr, and Salah El Deen A. Khamis

Abstract—The decoding of Downlink Control Information (DCI) in LTE is based upon a process that is defined as a blind decoding which depends on a number of decoding attempts on a number of Physical Downlink Control Channel (PDCCH) candidate locations for a number of defined DCI formats. In this paper, two proposed designs for DCI decoder are presented. The first decodes based upon monitoring PDCCH candidate locations serially. This design can perform the whole 44 decoding attempts within 87.3 % of the whole OFDM symbol time with extended cyclic prefix. So, it's well suited for Multicast/Broadcast over Single Frequency Network (MBSFN) subframes. However, this design doesn't meet the worst-case time of an LTE OFDM symbol with normal cyclic prefix. Therefore, a second design is proposed that exploits parallelism to enable fast blind decoding process. The proposed parallel design proves efficiency in meeting decoding time constraints besides, consuming a little power with a proven efficiency in utilization area perspective. The proposed parallel design performs all of 44 decoding attempts in a time of 7.8 μs which is only 11.7 % of an LTE useful OFDM symbol time with a logic power consumption of only 17000 μW. The proposed designs are simulated using Modelsim 6.4a and implemented in Plan Ahead 14.4 in 28 nm technology, Virtex7 FPGA kit of part number XC7V2000T, which is characterized by high performance and large capacity.

Index Terms—LTE, UESSS, CSS, DCI, PDCCH, UE.

Mohamed S. Abo Zeid, Mohamed E. Nasr, and Salah El Deen A. Khamis are with Electronics and Electrical Communications Dept., Faculty of Engineering, Tanta University, Tanta and 31527, Egypt (e-mail: m1_saeed@yahoo.com, salah.khamis@f-eng.tanta.edu.eg, mnasr@feng. tanta.edu.eg).
Khaled M. Elsayed is with Electronics and Electrical Communications Dept., Faculty of Engineering, Cairo University, Giza and 12613, Egypt (email: author@lamar. colostate.edu).

[PDF]

Cite:Mohamed S. Abo Zeid, Khaled M. Elsayed, Mohamed E. Nasr, and Salah El Deen A. Khamis, "Efficient Design and Implementation of LTE Downlink Control Information Decoder," International Journal of Computer Theory and Engineering vol. 6, no. 2, pp. 160-169, 2014.


Copyright © 2008-2024. International Association of Computer Science and Information Technology. All rights reserved.