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General Information
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2012 Vol.4(4): 611-615 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2012.V4.542

Augmenting Computer Architecture Classroom Experience with FPGAs Based Learning

Hasan Krad and Aws Yousif Fida El-Din
Abstract—Computer architecture is often taught by using software to design and simulate hardware modules and then using individual components to implement them. Our aim in this paper is to share our teaching experience of this subject in a way to enhance student learning outcome by developing projects for the computer architecture lab to help students better understand the theoretical concepts of the subject and to gain hands-on type of experience and apply that for more realistic projects. As a result, we have noticed that students show better interest in learning and understanding the subject materials over the last few semesters. We present in this work an ALU computer module design exercise as we used it in our computer architecture course. This approach can be well adopted for a first course in digital logic design, computer organization, and/or computer architecture. In specific, we designed and implemented an 8-bit arithmetic and logic unit, which performs 14 different arithmetic and logic operations. We did the design, simulation, and FPGA-based implementation of the proposed ALU module using QUARTUS II design software and Altera DE2 FPGA Board.

Index Terms—Computer architecture education, FPGA, VHDL, ALU, hardware modeling.

The authors are with the Department of Computer Science and Engineering, College of Engineering, Qatar University, Qatar (e-mail: hkrad@qu.edu.qa, altaie@qu.edu.qa).


Cite: Hasan Krad and Aws Yousif Fida El-Din, "Augmenting Computer Architecture Classroom Experience with FPGAs Based Learning," International Journal of Computer Theory and Engineering vol. 4, no. 4, pp. 611-615, 2012.
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