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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2012 Vol.4(1): 98-102 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2012.V4.432

A P System Simulator for Logic Gates

Amged Fathey, Amr Badr, and Ibrahim Farag
Abstract—The objectives of this paper are representing a simulator for the logic gates using P systems with priorities rules, and making use of the P system parallel computing in order to reduce the time used to test or evaluate a logic circuit (set of logic gates), which may change the vision of the current logic gates systems. Also, introducing the basic logic gates and how they work together, the development of the appropriate P system models for these gates are represented, and putting all together in order to get logic circuits which are P system based, finally a simulation and a test for them using a P Lingua language simulator, and an example is introduced to illustrate and making test of the model.

Index Terms—Logic gates, membrane computing, p-lingua, p system, simulator.

The authors are with the Computer Science Department, Faculty of Computers Science, MTI University, Cairo, Egypt (e-mail: amged_fathey@hotmail.com).

[PDF]

Cite: Amged Fathey, Amr Badr, and Ibrahim Farag, "A P System Simulator for Logic Gates," International Journal of Computer Theory and Engineering vol. 4, no. 1, pp. 98-102, 2012.
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