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General Information
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2011 Vol.3(4): 494-498 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2011.V3.356

ASIC Implementation of Neural Network Based Image Compression

K.Venkata Ramanaiah and Cyril Prasanna Raj
Abstract—Image data consumes enormous bandwidth and storage space. Neural networks can be used for image compression. Neural network architectures have proven to be more reliable, robust, and programmable and offer better performance when compared with classical techniques. In this paper the main focus is development of new architectures for neural network based image compression optimizing area, power and speed as specific to ASIC implementation, and comparison with FPGA. The proposed architecture designs are realized on Spartan IIIE FPGA Using Xilinx ISE, and the ASIC implementation is carried out using Synopsys tools targeting 130nm TSMC Library. The ASIC implementation for 2 input and 16 input neuron with low power techniques adopted such as buffer insertion, clock gating etc,

Index Terms—Image compression, neural networks, FPGA, ASIC, CSD

K.Venkata Ramanaiah, Principal, Narayana Engineering College Gudur, Andhra Pradesh, India
C. P. Raj,Course Manger M.S. Ramaiah School of Advanced Studies Bangalore, Karnataka, India


Cite: K.Venkata Ramanaiah and Cyril Prasanna Raj, "ASIC Implementation of Neural Network Based Image Compression," International Journal of Computer Theory and Engineering vol. 3, no. 4, pp. 494-498, 2011.

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