Abstract—Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents the design of a multiple-valued half adder and full adder circuits. The proposed adders are implemented in Multiple-Valued voltage-Mode Logic (MV-VML). In quaternary half adder, quaternary logic levels are first converted to binary and binary logic levels are used for the purpose of addition. Addition operation is performed with less number of gates and minimum depth of net. A full adder circuit is designed by converting the quaternary logic in to unique code, which enables to implement circuit with reduced hard ware. Sum and carry are processed in two separate blocks, controlled by code generator unit. Simple pass transistors are used for implementation. The design is targeted for the 0.18 µm CMOS technology and verification of the design is done through HSPICE and COSMOSCOPE Synopsis Tools. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less. Intensive simulation on Hspice also shows high performance of the proposed circuits.
Index Terms—Down literal circuit, multi-level logic, quaternary full adder, quaternary half adder
Vasundara Patel K S is with the Department of Electronics and Communication Engineering, BMS College of Engineering, (Vishwesvaraiya Technological University), Basavanagudi, Bangalore, 560019, Karnataka, INDIA, Phone, 9945217699, e-mail: firstname.lastname@example.org).
K S Gurumurthy, is with the Department of Electronics and Communication Engineering, University Vishwesvaraiya College of Engineering, (Bangalore University), K. R Circle, Bangalore, 560001, Karnataka, INDIA, 9945217699, e-mail: drksgurumurthy@ gmail.com).
Cite: Vasundara Patel K S and K S Gurumurthy, "Design of High Performance Quaternary Adders," International Journal of Computer Theory and Engineering vol. 2, no. 6, pp. 944-951, 2010.