Abstract—As embedded memory area on-chip is increasing and memory density is growing, problem of faults is growing exponentially. Considering the increasing impact that memory yield has on SoC yield in today's memory dominant SoCs, a high memory yield is required for acceptable levels of SoC yield. Thus memory fault modeling, detection and repair has come to take an important place. The architecture presented in this work implements the newly defined March SS algorithm which helps in detecting some recently modeled faults. Also, a word-oriented memory Built-in Self Repair methodology, which supports on-the-fly memory repair, is employed to repair the faulty locations indicated by the MBIST controller presented.
Index Terms—Built-In Self Test (BIST), Built-In Self Repair (BISR), Defect-Per Million (DPM), Memory Built-in Self Test (MBIST), Microcoded MBIST, Memory Built-In Self Repair (MBISR).
Dr. R. K. Sharma and Aditi Sood are with the Department of Electronics and Communications Engineering, National Institute of Technology, Kurukshetra (email: mail2drrks@gmail.com, aditi.vlsi@gmail.com).
Cite: R. K. Sharma and Aditi Sood, "Modeling and Simulation of Multi-Operation Microcode-based Built-in Self Test for Memory Fault Detection and Repair," International Journal of Computer Theory and Engineering vol. 2, no. 4, pp. 466-472, 2010.
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