doi: 10.7763/IJCTE.2011.V3.373
Modified Architectural Support to Implement Tomasulo’s Algorithm on Tournament Branch Predictor
Rubina Khanna
,
Vinay Chopra ,
Sweta Verma
Abstract
This paper proposes modified architecture of 21264, Out-Of-Order, six-way issue microprocessor. The proposed modified architecture implements Tomasulo’s algorithm using tournament branch prediction scheme to improve the performance of processor. Tomasulo's Algorithm controls the operation of the Common Data Bus (CDB) by means of tag mechanism. A tag is a 4-bit number used to identify separately each of eleven sources which can feed the CDB. The proposed modified architecture will evaluate branch outcome by taking both local and global history. The choice of global-versus-local branch prediction is made dynamically on a path-based predictor that decides which predictor to use, based on the past correctness of choice.
Keywords
- common data bus (CDB)
- tomasulo’s algorithm
- tournament branch predictor
How to Cite
Rubina Khanna, Vinay Chopra, and Sweta Verma, "Modified Architectural Support to Implement Tomasulo’s Algorithm on Tournament Branch Predictor," International Journal of Computer Theory and Engineering, vol. 3, no. 4, pp. 575-578, 2011. https://doi.org/10.7763/IJCTE.2011.V3.373
Copyright & License
Copyright © 2011 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).