Abstract—This paper proposes an efficient strategy to implement modified non restoring algorithm based on FPGA in gate level abstraction of VHDL, which adopt fully pipelined architecture. A new basic building block is called controlled subtract-multiplex (CSM) is introduced. The main principle of the proposed method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The proposed strategy has conducted to implement FPGA successfully, and it is offer an efficient in hardware resource.
Index Terms—FPGA, non-restoring, Gate Level, square root
Tole Sutikno is with the Department of Electrical Engineering, Universitas Ahmad Dahlan (UAD), Yogyakarta, Indonesia, e-mail: thsutikno@ieee.org, tole@ee.uad.ac.id.
[PDF]
Cite: Tole Sutikno, "An Efficient Implementation of the Non Restoring Square Root Algorithm in Gate Level,"
International Journal of Computer Theory and Engineering vol. 3, no. 1, pp. 46-51, 2011.
