DOI: 10.7763/IJCTE.2010.V2.221
Memory Reduced and Fast DDS Using FPGA
Abstract—Direct digital synthesis is a method of creating arbitrary waveforms of desired frequency. A general DDS system comprises analog and digital part. Phase accumulator and LUT make digital part and DAC makes analog part. This paper presents 12 bit memory reduced FPGA based architecture of DDS. Phase truncation and quadrature symmetry of sine wave are used to achieve higher ROM compression. Dither is also used to achieve error free output. This design has been implemented on SPARTAN-3E FPGA with maximum clock frequency of 50 MHz. We have used LTC 2624 quad DAC with 12 bit resolution which introduces very less amount of harmonics hence LPF is not needed. This design uses only 128 memory locations. Hence it is suitable for applications where system speed, memory and size of the systemare main concern. Its wide and flexible range of frequency make it useful in RF transmission, Biomedical function generators and Modulation.
Index Terms—Direct digital synthesis (DDS), Phase truncation, ROM compression
Dr. R. K. Sharma, Associate Professor, is with NIT Kurukshetra, Haryana, India (+919896688346; e-mail: mail2drrks@gmail.com).
Gargi Upadhyaya, Adhok lecturer is with NIT Kurukshetra, Haryana (+919466751547: e-mail: gargi.mbd@gmail.com).
Cite: R. K. Sharma and Gargi Upadhyaya, "Memory Reduced and Fast DDS Using FPGA," International Journal of Computer Theory and Engineering vol. 2, no. 4, pp. 670-672, 2010.