doi: 10.7763/IJCTE.2010.V2.186
Modeling and Simulation of Multi-Operation Microcode-based Built-in Self Test for Memory Fault Detection and Repair
R. K. Sharma
,
Aditi Sood
- Department of Electronics and Communications Engineering, National Institute of Technology, Kurukshetra.
Abstract
As embedded memory area on-chip is increasing and memory density is growing, problem of faults is growing exponentially. Considering the increasing impact that memory yield has on SoC yield in today's memory dominant SoCs, a high memory yield is required for acceptable levels of SoC yield. Thus memory fault modeling, detection and repair has come to take an important place. The architecture presented in this work implements the newly defined March SS algorithm which helps in detecting some recently modeled faults. Also, a word-oriented memory Built-in Self Repair methodology, which supports on-the-fly memory repair, is employed to repair the faulty locations indicated by the MBIST controller presented.
Keywords
- Built-In Self Test (BIST)
- Built-In Self Repair (BISR)
- Defect-Per Million (DPM)
- Memory Built-in Self Test (MBIST)
- Microcoded MBIST
- Memory Built-In Self Repair (MBISR)
How to Cite
R. K. Sharma and Aditi Sood, "Modeling and Simulation of Multi-Operation Microcode-based Built-in Self Test for Memory Fault Detection and Repair," International Journal of Computer Theory and Engineering, vol. 2, no. 4, pp. 466-472, 2010. https://doi.org/10.7763/IJCTE.2010.V2.186
Copyright & License
Copyright © 2010 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).