General Information
    • ISSN: 1793-8201 (Print), 2972-4511 (Online)
    • Abbreviated Title: Int. J. Comput. Theory Eng.
    • Frequency: Quarterly
    • DOI: 10.7763/IJCTE
    • Editor-in-Chief: Prof. Mehmet Sahinoglu
    • Associate Editor-in-Chief: Assoc. Prof. Alberto Arteta, Assoc. Prof. Engin Maşazade
    • Managing Editor: Ms. Mia Hu
    • Abstracting/Indexing: Scopus (Since 2022), INSPEC (IET), CNKI,  Google Scholar, EBSCO, etc.
    • Average Days from Submission to Acceptance: 192 days
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Prof. Mehmet Sahinoglu
Computer Science Department, Troy University, USA
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.

IJCTE 2010 Vol.2(3): 333-337 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2010.V2.163

Realization of BCD adder using Reversible Logic

X. Susan Christina, M. Sangeetha Justine, K. Rekha, U. Subha and R. Sumathi

Abstract—This paper proposes novel carry select and carry look-ahead BCD adders using reversible logic. Reversible logic gates are widely known to be compatible with future computing technologies which virtually dissipate zero heat. Adders are fundamental building blocks in many computational units. For this reason, we have simulated several adder circuits using the reversible gates. Among all the other adders, the main virtue of BCD adders is that it allows easy conversion to decimal digits for printing or display and faster decimal calculations. These reversible BCD circuits are basis of the decimal ALU of primitive Quantum CPU. The proposed BCD adders have been simulated in VLSI and static timing report was analyzed.

Index Terms—Reversible logic gates, BCD adder , quantum computing.

X. Susan Christina, M. Sangeetha Justine, K. Rekha, U. Subha and R. Sumathi, department of Electronics and Communication Engineering Mookambigai College of Engineering , Pudukottai-60, India.


Cite: X. Susan Christina, M. Sangeetha Justine, K. Rekha, U. Subha and R. Sumathi, "Realization of BCD adder using Reversible Logic," International Journal of Computer Theory and Engineering vol. 2, no. 3, pp. 333-337, 2010.  

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