Abstract—Predicting status of registers is required in verification development to accurately emulate behaviors of DUT. However, it is a complicated thing when register couplings exists in DUTs. To unleash verification development, we propose a graph-based solution, with a model of “topology + behavior” for register couplings, to accurate emulate states and behaviors of DUT. This work is inspired by realistic verification requirement in industry-level developments. With searching mechanism, register couplings can be efficiently and accurately processed at runtime. Verification works can be significantly simplified without remarkable resource costs and performance loss. Our experiment and analysis finally suggest tempting benefits of this method in functional verification development.
Index Terms—Chip development, functional verification, EDA.
Zhang Yuxuan, Jiang Guofan, Lu Yinchao, and Gou Pengfei are with China System and Technology Laboratory, IBM, Shanghai, P.R. China (e-mail: {zyxsh, jianggf, luyinch, goupengf}@cn.ibm.com).
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Cite:Zhang Yuxuan, Jiang Guofan, Lu Yinchao, and Gou Pengfei, "A Graph-Based Solution for Register Coupling in Functional Verification," International Journal of Computer Theory and Engineering vol. 8, no. 5, pp. 379-384, 2016.
