Abstract—The layout between the processor and memory in parallel bus is very complex and difficult to place and route. The expansion of memory capacity and bandwidth is limited. A new memory system using an optical connection is proposed. We designed a serial interface using packet communication, and implemented a protocol engine to be executed on the interface. To test the feasibility of the protocol engine, we implemented a video system using an embedded processor on FPGA. The master and slave protocol engines were on the same FPGA, but used the clock differently. We conducted an experiment on the function of the proposed protocol engine between the video frame buffer and memory using a 2×10-Gbps serial link.
Index Terms—Memory channel, protocol, main memory.
Hyukje Kwon and Yongseok Choi are with the Electronics and Telecommunications Research Institute, Korea (e-mail: {heavenwing, shine24}@etri.re.kr).
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Cite:Hyukje Kwon and Yongseok Choi, "Feasibility Test of Protocol Engines for a New Video System in Packet Communication," International Journal of Computer Theory and Engineering vol. 8, no. 3, pp. 207-212, 2016.
