doi: 10.7763/IJCTE.2016.V8.1045
Feasibility Test of Protocol Engines for a New Video System in Packet Communication
Hyukje Kwon
,
Yongseok Choi
- Electronics and Telecommunications Research Institute, Korea.
Abstract
The layout between the processor and memory in parallel bus is very complex and difficult to place and route. The expansion of memory capacity and bandwidth is limited. A new memory system using an optical connection is proposed. We designed a serial interface using packet communication, and implemented a protocol engine to be executed on the interface. To test the feasibility of the protocol engine, we implemented a video system using an embedded processor on FPGA. The master and slave protocol engines were on the same FPGA, but used the clock differently. We conducted an experiment on the function of the proposed protocol engine between the video frame buffer and memory using a 2×10-Gbps serial link.
Keywords
- Memory channel
- protocol
- main memory
How to Cite
Hyukje Kwon and Yongseok Choi, "Feasibility Test of Protocol Engines for a New Video System in Packet Communication," International Journal of Computer Theory and Engineering, vol. 8, no. 3, pp. 207-212, 2016. https://doi.org/10.7763/IJCTE.2016.V8.1045
Copyright & License
Copyright © 2016 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).