DOI: 10.7763/IJCTE.2014.V6.906
Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network
Abstract—This paper presents a low power asynchronous
10-bit Successive Approximation Register (SAR) ADC
implemented in 0.18μm CMOS process. The ADC is realized
fully differentially with a split capacitor array to lower power
cost and improve the speed. To further enhance power
efficiency and high speed for a relatively moderate resolution,
a new asynchronous dynamic logic is utilized to lower the
digital power. The multiple-phase clock is generated by a
ring-oscillator structure which avoids the high external clock.
Offset of the dynamic clocked-comparator is also calibrated
through adjusting the threshold voltage. The ADC consumes
500uw at Vdd=1.8v and 10M/s sampling rate.
Index Terms—SAR analog to digital converter (ADC), low
power, fully dynamic comparator, CMOS, offset cancellation,
asynchronous logic.
The authors are with the Institute of Microelectronics, Chinese Academy
of Science (IMECAS), NO. 3 Beitucheng West Road, 100029, Beijing
(e-mail: zhangyulin@ ime.ac.cn).
Cite:Yulin Zhang, Guiliang Guo, Yuepeng Yan, and Tao Yang, "Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network," International Journal of Computer Theory and Engineering vol. 6, no. 6, pp. 443-446, 2014.