Abstract—High performance DSP processors are unable to
meet the speed requirements of Software Defined Radio (SDR),
System on chips (SOCs) are also not suitable because of their
limited flexibility. Recently dynamically reconfigurable FPGAs
have emerged as high performance programmable hardware to
execute highly parallel, computationally intensive signal
processing functions efficiently. Since basic intention of SDR is
to implement different modulation or demodulation schemes
and basic building blocks for these schemes are signal
processing functions, FPGAs have become an important
platform for implementing SDR. Keeping these issues in view,
this paper proposes a flexible architecture that combines five
different modulation schemes. FPGA based implementation of
the proposed architecture reveals that the number of LUTs is
reduced by 11.11% compared to the sum of individual LUTs
used for each of the modulation scheme. Not only LUTs but also
other FPGA components like slices, bounded IOB, BESL etc.
are also reduced.
Index Terms—Application specific integrated circuits
(ASIC), configurable logic block (CLB), common block
diagram elimination method (CBDEM), communication
schemes, digital signal processor (DSP), field programming gate
array (FPGA), hardware description language (HDL), look up
table (LUT), software defined radio(SDR), silicon utilization
factor.
A. Karmakar is with the West Bengal University of Technology in the
Department of Computer Science of Engineering, BF-142, Sector 1, Salt
Lake City (e-mail: amiya.karmakar@gmail.com).
A. Saha is with the Department of Electronics & Communication
Engineering, Neotia Institute of Technology Management & Science
Institution affiliated to West Bengal University of Technology and AICTE
approved Degree College. Campus: Sarisa, Diamond Harbour Road, South
24 parganas, West Bengal (e-mail: inchargetandp@nitmas.edu.in).
A. Sinha is with Neotia Institute of Technology Management & Science
Institution affiliated to West Bengal University of Technology and AICTE
approved Degree College as a Principal. Campus: Sarisa, Diamond Harbour
Road, South 24 parganas, West Bengal (e-mail:
amitabha.sihna@wbut.edu.in or principal@nitmas.edu.in).
[PDF]
Cite:Amiya Karmakar, Amrita Saha, and Amitabha Sinha, "On the Design of a Reconfigurable Radio Processor Using FPGA," International Journal of Computer Theory and Engineering vol. 6, no. 2, pp. 81-85, 2014.
