General Information
    • ISSN: 1793-8201 (Print), 2972-4511 (Online)
    • Abbreviated Title: Int. J. Comput. Theory Eng.
    • Frequency: Quarterly
    • DOI: 10.7763/IJCTE
    • Editor-in-Chief: Prof. Mehmet Sahinoglu
    • Associate Editor-in-Chief: Assoc. Prof. Alberto Arteta, Assoc. Prof. Engin Maşazade
    • Managing Editor: Ms. Mia Hu
    • Abstracting/Indexing: Scopus (Since 2022), INSPEC (IET), CNKI,  Google Scholar, EBSCO, etc.
    • Average Days from Submission to Acceptance: 192 days
    • APC: 800 USD
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Prof. Mehmet Sahinoglu
Computer Science Department, Troy University, USA
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.

IJCTE 2019 Vol.11(6): 112-115 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2019.V11.1253

The Compatibility Analysis of AES Algorithm for Design Portability on FPGA

S. J. H. Pirzada, A. Murtaza, T. Xu, and L. Jianwei

Abstract—The increase in utilization of digital systems for rapid prototyping has compelled researcher to use Field Programmable Gate Array (FPGA) hardware. The Hardware description language (HDL) such as Verilog and VHDL, etc. are utilized for designing digital systems on FPGA. The HDL core can be designed either by the designing a core by indivisual or by using the ready-to-use cores provided by FPGA vendors. The cores provided by FPGA vendors are Intellectual Property core (IP-core) which provides an rapid prototyping option for implementation on FPGA. The IP-core provided by one FPGA vendor cannot be used on other vendors FPGAs. Therefore, designing an HDL core by indivisual provides the design portability on FPGA, as the core designed by indivisual can be used on FPGA of any vendor. Therefore, in scenarios where it is required to have FPGA platform independent solution, an individual designed HDL core is highly recommended instead of IP-core provided by FPGA vendors. Moreover, the licensing is required for many IP-cores; which makes it less feasible for low-cost design as licensed IP-core are available on payment. In this work, the Advanced Encryption Standard (AES) algorithm HDL core design is compared between HDL core designed by individual and IP-core provided by different FPGA vendors. Experimental results show that the comparison of implementations present quite similar results; however, design portability of an HDL core designed by an individual makes it more attractive in contrast to that is available by FPGA vendors.

Index Terms—Advanced encryption standard, field programmable gate array, hardware description language, intellectual property core.

S. J. H. Pirzada, T. Xu, and L. Jianwei are with the School of Cyber Science and Technology, Beihang University, Beijing, China (e-mail: jahanzebp@,, A. Murtaza is with the School of Electronics and Information Engineering, Beihang University, Beijing, China (e-mail:


Cite:S. J. H. Pirzada, A. Murtaza, T. Xu, and L. Jianwei, "The Compatibility Analysis of AES Algorithm for Design Portability on FPGA," International Journal of Computer Theory and Engineering vol. 11, no. 6, pp. 112-115, 2019.

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