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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2012 Vol.4(5): 831-834 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2012.V4.588

3D Device Modeling and Assessment of Triple Gate SOI FinFET for LSTP Applications

Kiran Bailey and K. S. Gurumurthy

Abstract—The FinFET is a very good candidate for future VLSI due to its simple architecture and better performance when compared to SOI MOSFET. SGOI (Silicon Germanium on Insulator) Recessed Source drain MOSFETs and SOI FinFETs are analyzed by a commercial 3-D device simulator. It is shown that SOI FinFET with Thin Fin widths compared to SGOI MOSFETs Body thicknesses, have better control over short channel effects (SCEs) and reduced power dissipation due to reduced gate leakage currents. By varying the spacer width and the Fin width, device performance is found to improve. The performance of triple gate FinFET has been compared with that of Ultra-Thin Body (UTB) Recessed Source drain SGOI MOSFET in terms of delay, power consumption and noise margin for a CMOS inverter and results indicate the better suitability of SOI FinFET structures for Low standby Power(LSTP) Applications. The SOI FinFET device Sensitivity to process parameters such as Gate Length, Spacer Width, Oxide thickness, Fin Width, Fin Height and Fin doping has been examined and reported.

Index Terms—DIBL, SOI FinFET, SGOI recessed sourcedrain MOSFET, SCEs, subthrehold slope, static power dissipation.

Kiran Bailey is with the the dept. of E&C, BMSCE, Bangalore.
K. S. Gurumurthy is with the DOS in E & CE Dept., UVCE, Bangalore University, Bangalore.

[PDF]

Cite: Kiran Bailey and K. S. Gurumurthy, "3D Device Modeling and Assessment of Triple Gate SOI FinFET for LSTP Applications," International Journal of Computer Theory and Engineering vol. 4, no. 5, pp. 831-834, 2012.

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