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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2012 Vol.4(5): 812-815 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2012.V4.584

Improvement of Optimization in Design of Synchronous Sequential Circuits by Using Evolvable Hardware

P. Soleimani, S. Mirzakuchaki, R. Sabbaghi-Nadooshan, and M. Bagheri

Abstract—Evolvable hardware is a new method for designing the digital logic circuits. In this paper, a method has been presented for designing the synchronous sequential logic circuit by using the evolvable hardware. In this approach, the sequential logic circuit is divided into two sections; the combinational logic circuit and DFFs. The combinational logic part is designed by using a constant structure and their connections are set with genetic algorithm (GA). The results show that our method can reduce the average number of generations by limitation the search space.

Index Terms—Sequential circuit, combinational circuit, genetic algorithm, evolvable hardware, evolutionary algorithm.

P. Soleimani and R. Sabbaghi-Nadooshan are with the Department of electronic engineering, Islamic Azad University, Central Tehran Branch (e-mail: parisa.soleimani@ gmail.com, r_sabbaghi@iauctbt.ac.ir).
S. Mirzakuchaki and M. Bagheri are with the Department of electronic engineering, Iran University, of Science and Technology (e-mail: M_kuchaki@iust.ac.ir, m-bagheri@elec.iust.ac.ir).

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Cite: P. Soleimani, S. Mirzakuchaki, R. Sabbaghi-Nadooshan, and M. Bagheri, "Improvement of Optimization in Design of Synchronous Sequential Circuits by Using Evolvable Hardware," International Journal of Computer Theory and Engineering vol. 4, no. 5, pp.  812-815, 2012.

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