Abstract—The relevance of VLSI in performance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. In order to build complex digital logic circuits it is often essential to sub-divide multi million transistors design into manageable pieces.Circuit partitioning is a general approach used to solve problems that are too large and complex to be handled at once. In partitioning, the problem is divided into small and manageable parts recursively, until the required complexity level is reached. In the area of VLSI, circuit complexity is rapidly multiplying together with the reducing chip sizes, the integrated chips being produced today are highly sophisticated. There are many diverse problems that occur during the development phase of an IC that can be solved by using circuit partitioning which aims at obtaining the sub circuits with minimum interconnections between them. This paper aims at circuit partitioning of VLSI application using classification techniques, that is, Decision Tree Algorithm and K-Nearest Neighbors Algorithm. These two algorithms were tested for partitioning optimization on a 3-bit Priority Encoder and a 4x2 SRAM sample circuits and implemented using VHDL. The tested results shows that the K-Nearest Neighbor algorithm yields better subcircuits than the Decision Tree Algorithm.
Index Terms—Circuit Partitioning, Decision Tree Classification Algorithms, K-Nearest Neighbor algorithm
Dr. Sumithra devi K. A. Member, IACSIT No. 80334046
Vijayalakshmi M. N. Member, IACSIT 80332289
Cite: Dr. Sumithra devi K. A. and Vijayalakshmi M.N., "Classification Algorithms in Achieving Partitioning Optimization for VLSI Applications," International Journal of Computer Theory and Engineering vol. 2, no. 6, pp. 916-918, 2010.