Abstract—Different logic gates like MV, NOT, AOI, NNI etc under QCA nanotechnology are introduced. NNI gate is highly effective regarding space and speed consideration. Any Boolean functions, confined in thirteen number standard Boolean functions, are synthesized by MV and NNI gates or simply NNI gates alone, eliminating inverter (NOT) gate. A new method for realizing symmetric functions in binary reversible logic is introduced. My procedure synthesizes for amore efficient realization both the unate and non unate symmetric functions with little “garbage”. The method is used in a classical logic. I use only 2-inputs and 2-outputs ANDNAND and OR-NOR cells designed on QCA technology. It admits a recursive construction. Ultimately I achieve a general equation for the minimum number of gates required to an arbitrary number of input variables, causing synthesis of symmetric function. These symmetric functions consist of different Boolean functions with adder circuits functions, subsequently all other combinational circuits like subtractor, multiplier, divisor, multiplexer, encoder, comparator etc can be designed by the adder circuit only which ensures next generation IC design. It provides a significant reduction in hardware cost and switching delay compared to other existing techniques.
Index Terms—Majority Voter (MV) gate, And-Or-Inverter (AOI) gate, Nand-Nor-Inverter (NNI) gate, 2-Inputs and 2-Outputs AND-NAND (A-NA) gate, 2-Inputs and 2-Outputs OR-NOR (O-NO) gate, Symmetric Function.
Pijush Kanti Bhattacharjee is an Assistant Professor in the Department of Electronics and Communication Engineering, Bengal Institute of Technology and Management, Santiniketan, P.O. Doranda, West Bengal, Pin-731236, India.
Cite: Pijush Kanti Bhattacharjee, "Use of Symmetric Functions Designed by QCA Gates for Next Generation IC," International Journal of Computer Theory and Engineering vol. 2, no. 2, pp. 211-217, 2010.