Design of Ethernet-VLC Data Conversion System Based on FPGA

in the Ethernet-VLC buffer logic, the visible light communication transceiver logic framing and sent frame to optical path. In the uplink, the GTP transceiver receives the data from the optical path, performs de-frame processing through the transceiver logic, and sends the data to the VLC-Ethernet buffer logic to speed up to Gigabit. And


I. INTRODUCTION
Wireless communication technology is widely used in our lives. As an emerging technology, visible light communication (VLC) is gradually entering the field of academics. Along with the popularization of solid-state lighting, LED (Light Emitting Diode) has been applied to a large area. The Visible Light Communication uses LED as carrier, and uses electromagnetic wave in the visible light band as a carrier to modulate data information onto visible light, thereby achieving communication through it. Most of visible light communication researches focus on the point-to-point transmission in LOS (Line-of-sight) case [1]. Visible Light Communication doesn't occupy scarce radio spectrum and can be used without any license [2].
At present, research on visible light communication mostly focuses on material research [3], coding methods [4], modulation methods [5], and equalization methods [6]. Research focuses more on increasing transmission rates [7]. There are less researches on application. Some researches use Manuscript  then the 8-bit data is restored by the bit-width conversion logic. Finally, the frame is issued via the Ethernet interface.

A. Ethernet Interface Logic
The Ethernet interface logic completes the establishment of the communication interface and the configuration of the PHY chip. The functional diagram of the module is shown in Fig. 2. This interface logic design based on RGMII consists of three parts, i.e., SMI (Serial Management Interface), RX, and TX. SMI logic configures the registers in the Ethernet PHY layer slave through the MDC and MDIO interfaces to implement reset and auto-negotiation functions. When the auto-negotiation succeed, Ethernet interface logic will be enabled. RX logic receives the Ethernet data, removes the frame header, and sends data information to bit-width conversion module after performing the CRC (Cyclic Redundancy Check) [14]. TX logic receives data sent from bit width conversion logic for new framing transmission. The frame interval needs to meet the minimum frame interval of the Ethernet in the process of transmission. The minimum frame interval of Gigabit Ethernet is 96 ns, and one clock is configured for 8 ns. When the interval time satisfies 12 clocks, the time is to enable signal. And the previous logic starts to send the package, otherwise the signal will be set low.

B. Bit-width Conversion Logic
Because the design use GTP transceivers which only support 16-bit and 32-bit width data, we should perform width conversion. Considering that high bit width can reduce the frequency of the synchronous clock, this paper use 32-bit width. The bit width conversion logic is based on pseudo-dual-port RAM (Random Access Memory). The downlink writing bit-width is 8, the readout bit-width is 32, the uplink writing bit-width is 32, and the readout bit-width is 8. The uplink and downlink writing and readout operations are similar. Here we take an 8-bit to 32-bit module as an example.
In order to facilitate reading and writing, three address pointers are defined. The pointer WP (write pointer), write data with 8-bit width to RAM in ascending order of address. When writing the last byte of data frame, the first write address of the next frame is determined according to the length of the data frame. When the frame length is a multiple of 4, WP increases normally. When the frame length is not a multiple of 4, WP go to the next address that is a multiple of 4. The pointer RP (read pointer), read 4 bytes of data from high to low at a time. The pointer VP (valid pointer), will be determined if the received data frame check value is correct. If the frame writing into buffer is correctly verified, VP will go to the current position of WP. If the frame writing into buffer is incorrectly verified, WP will be returned to the current VP position.
The maximum byte-length of the Ethernet frame is 1518 and the minimum byte-length is 64. In order to satisfy the requirement of storing one frame of data, the capacity of the RAM is at least 2048 bytes (16384 bits). So the RAM capacity is 16Kb. In order to avoid the conflict when the address is read and written at the same time, the WP will be turned on after the full frame is written completely. However, when the previous frame is reading, the next frame is written completely, e.g. when after the frame A of length 1518 bytes is written, a frame B of length 64 bytes is written. The frame B is written during the reading of the frame A. But at this time, there is no logic to lay in the length information of frame B. Therefore, a FIFO (First Input First Output) storing length information is added to cooperate with the RAM to perform bit-width conversion. Considering that the capacity of the RAM is 2048 bytes, the FIFO bit-width is 11 and the bit-depth of the FIFO is 32 (2048 bytes/64 bytes).
Taking one frame as an example. The frame is written to the RAM according to the writing-enable signal. And then frame checked by CRC. If the result is correct, the signal will be pulled up raised one clock. The length information will be stored into the FIFO and VP go to WP. If the result is error, the writing-enable signal does not pull up, then WP will go to VP. The timing diagram for the writing operation is shown in Fig.  3. Frame readout based on FIFO status. Detect the status of FIFO. If FIFO is not empty, the reading process of one frame is started and the length information of the current frame is read from the FIFO. The reading timing diagram as shown in Fig. 4.

C. Buffer Logic
The buffer logic is the core of the system. The buffer in the uplink is responsible for slowing down the high-speed Ethernet data frames to the low-speed visible-light clock domain. In the downlink, the frame received from the visible light communication carried to the Ethernet clock domain. Thereby the logic implements two-way communication. The FIFO feature is suitable for buffers, which can reduce the complexity of the design [15]. The uplink and downlink buffers are composed of two asynchronous FIFOs, namely, the DFIFO (Data FIFO) that stores the data frame and the IFIFO (Information FIFO) that stores the frame length information. High-speed data synchronization to low-speed clock is a design difficulty.
The data transmission process complies with the Ethernet TCP/IP protocol. And there is a timeout retransmission rule. After the transmitter sends out one frame, if the acknowledgment information fed back by the receiver is not received within a certain period of time, the transmitter will resend the data until the feedback is received. Because data is transmitted from high speed to low speed and the buffer will be full, discard of data frames is inevitable. But according to this rule, the receiver can receive the complete information correctly through the read-write control. The speed-down buffer is implemented based on this rule.
Depth calculation is very important to pass the data between different clock domains [16]. In downlink the deeper FIFO depth is better to use in speed-down buffer. Considering the device performance, the DFIFO bit-depth used in this paper is 8192 and the bit-width is 32. To better control the buffer capacity, the threshold is set in the buffer. The amount of DFIFO (dfifo_data_count) is maintained between upper threshold and lower threshold. The longest frame has a byte-length of 1518, and a bit-depth of 190 in buffer. The shortest frame has a byte-length of 64, and a bit-depth of 190 in buffer. Considering the situation of continuously writing the longest frame, the upper threshold should ensure that the buffer is not full. The upper threshold is set to 7811 (8191-190*2). The lower threshold keeps FIFO at half full state, and is set to 3715 (4095-190*2). In uplink, the data pass through the buffer from low speed to high speed. There is no data congestion. When the back-to-back transmission is satisfied, two 1518-byte frames are continuously received. Since the FIFO depth is 2 n , it takes 4096 bytes and the bit-width is 32, so the bit-depth is 1024. The speed-up buffer IFIFO may approach the full state due to a large number of 64-byte frames are written. To avoid the IFIFO being full, upper threshold is set to 495 (511-8*2), and the lower threshold is set to 8.
The writing process flowchart is shown in Fig. 5. When the dfifo_data_count surpass the upper threshold, the writing-enable signal is turned off to stop writing. At this time, the buffer is only readout enabled. When the dfifo_data_count falls to the lower threshold, the writing-enable signal is enabled to continue writing data.
The data readout process is shown in Fig. 6. When the data in the IFIFO is not empty, the length information will be read, and the data frame will be read according to data length. If IFIFO is empty and DFIFO is non-empty, it indicates that data fragments exist in DFIFO. Currently, stop writing to clear FIFO, and rely on this fragment cleaning mechanism to ensure the integrity of data transmission.

D. Visible Light Communication Transceiver Logic
The visible light communication transceiver logic assembles the data information into an VLC frame and sends it to the visible light channel via FPGA integrated GTP transceiver. The data clock recovery is integrated inside the GTP transceiver receiver. The data frame structure used in this paper is shown in Fig. 7. The data frame is based on 8B/10B coding technology. High-speed data transmission or data bus often uses 8B/10B protocol [17]. The visible light communication uses OOK modulation. The 8B/10B coding has a level-balancing feature that ensures that the LED does not flicker. The 8B/10B encoded data is serialized and deserialized via GTP transceiver. The frame includes a frame synchronization code, a frame start delimiter, a frame load, and a frame check. After the bit-width conversion, the frame bit-width is 32, that is, 4 bytes of data are processed under the same clock edge. For each frame, a frame synchronization code (0xff0000bc) is sent, which marks the arrival of a frame. Frame start delimiter (0xffxxxxfb) contains the length information of the frame (xxxx is the length information), and the length range is from 0 to 65535. Then the frame load is sent, that is, the encapsulated frame carries the data information. A frame check is added after the data part is over, which is used by the receiver to check, filter, and remove the data frames that have errors during transmission. The frame check in solution uses CRC32. The calculation starts from the frame start code and stops at the end of the data part. There is a frame interval between data frames, where 0xbc is sent, corresponding to K28D5 of 8B10B. When the transmission is idle, the transmitter will continuously send K28D5, which provides the receiver with the function of calibration. The overall change process of the frame in the system is shown in the Fig. 8. The optical path can be easily affected by external interference which results in transmission interrupting. When the optical path is cut off, the receiver will detect a data error. But the transmitter still sent the data, so the data transmission is maintained. At this time, if the optical path is turned on again, the receiver may receive the frame from the middle position, and the communication may be break. In this case, a recovery mechanism is added to the transceiver logic. The receiver must check each frame to be received by the transceiver, and mark the wrong frame. When transmitting to the subsequent logic, the frame will be masked. Normal data transmission is resumed when reconnected.

III. SIMULATION AND EXPERIMENT RESULT
First, the feasibility of the system design is verified through simulation. In the simulation, the transmitter and the receiver of the optical path are connected. Fig. 9 and Fig. 10 are the simulation diagrams of the Ethernet side transmitter and receiver. It can be seen that the data is looped back and the result is correct.  In the system experiment, the VLC side interface is connected to the oscilloscope, and the other side is connected to the Ethernet. The waveform can be observed by the oscilloscope, as shown in Fig. 11. It is verified that the system reaches the rate of 625Mbps. In the functional experiment, since the network cannot reach the full-speed Gigabit network in the general environment, a Gigabit Ethernet packet generator is used for the experiment. The packet generator can send data frames with a byte length of 64 to 1518 at full speed. The test environment diagram is shown in Fig. 12. The packet generator sends data to System 1. After the data is converted, it is sent to the System 2 by VLC. After System 2 receives the data, it returns data back to Ethernet and sends it to PC. PC uses the traffic monitoring software NerPerSec to detect the network speed. The network speed is shown in Fig. 13. The transmission rate is close to 500Mbps. Because the system uses 8B/10B encoding and decoding, the ratio between the data rate on the optical path after encoding and the data rate on Ethernet before encoding should be 5: 4. The 625Mbps rate on optical path corresponds to the 500Mbps Ethernet rate. After the optical path is cut and reconnected, the system has restored the data connection, as shown in Fig. 14.   International Journal of Computer Theory and Engineering, Vol. 12, No. 3, June 2020 IV. CONCLUSION In this paper, we propose a design of an Ethernet-VLC data conversion system, which can realize the conversion between Gigabit network and 625Mbps optical data. We define the structure of the system and the functions of each module. Through simulation and experiments, we proved the feasibility of the system. And in order to improve the stability of the system, we defined the data frame structure and added recovery system at the receiver. Next, further research will be conducted in the areas of system buffer control and multi-user.