Abstract—Integrating numerous cores of different types into an SOC, makes the test process a complex activity. The need for a standard test infrastructure has led to the development of IEEE Std 1500 which is a modular and scalable test interface, enables test and diagnosis of embedded cores and interconnect. Although this standard can drastically simplify test challenges of SOCs, its hardware architecture, usually called wrapper, may occupy a noticeable silicon area when used for memory cores. In this paper, we present a specialized wrapper for memory cores compatible with IEEE Std 1500 which support parallel and at-speed testing of all memory cores with reasonable area overhead. We specially focus on the design of Wrapper Boundary Register which is mostly responsible for this overhead. Simulation and synthesis results on a group of embedded memory cores confirm that the proposed wrapper has been effectively reduced the area overhead.
Index Terms—Embedded memory testing, system-on-chip (SoC), built-in-self-test (BIST), IEEE Std 1500, wrapper boundary register (WBR).
M. Songhorzadeh is with the Department of Electrical Engineering at Shahid Chamran University of Ahvaz, Iran (e-mail: m.songhorzade@gmail.com).
R. Niaraki Asli is with the Electrical Engineering Department, University of Guilan, Guilan, Iran (e-mail: niaraki_asli@yahoo.com)
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Cite: M. Songhorzadeh and R. Niaraki Asli, "A Low Area Overhead IEEE-1500-Compliant Wrapper for Embedded Memories,"
International Journal of Computer Theory and Engineering vol. 4, no. 6, pp. 944-948, 2012.
