Abstract—In this paper, a VLSI architecture of turbo decoder employing an efficient stopping criterion is proposed. The new stopping criterion algorithm is based on Hard Decision Aided(HDA) stopping criterion algorithm, using phase estimation method to reduce iterations also improve turbo decoding efficiency. In high SNR environment, the proposed algorithm requires less iterations without losing error correction ability compared to traditional stop criteria algorithms. In addition, it can save power consumption due to decoding termination within single iteration. As for low SNR environment, we can stop iteration immediately when it detect the received data can not be decoded. The proposed algorithm can stop the turbo decoder earlier than traditional methods in both high SNR and low SNR environment. Finally, for verifying the proposed algorithm, a turbo decoder using new phase estimation is designed with TSMC 0.18μm 1P6M process, the chip size is 1530μm 1504μm and working frequency is 48MHz.
Index Terms—Turbo decoder, stopping criterion, phase estimation, hard decision.
Wen-Ta Lee is with the Department of Electronic Engineering, National Taipei University of Technology (e-mail: firstname.lastname@example.org Wen-Ta Lee).
Yao-Chang Chang is with the Institute of Computer and Communication from National Taipei University of Technology.
Cite: Wen-Ta Lee and Yao-Chang Chang, "Turbo Decoder Design Employing a New Phase Estimation Hard Decision Stopping Criterion Method," International Journal of Computer Theory and Engineering vol. 4, no. 6, pp. 963-966, 2012.