Abstract—Leakage currents in deep sub-micrometer regimes is becoming a significant contributor to power dissipation in CMOS digital circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Therefore, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power consumption, especially for battery powered and portable low-power applications. In this work we have performed an analysis and circuit level simulation at Deep Sub-Micron (DSM) Complementary Metal Oxide Semiconductor (CMOS) technology, pdk45nm. The simulation has been performed on the existing Static Random Access Memory (SRAM) cell structures, e.g., the conventional 6T, PP, P4, P3, and IP3 cells, to calculate the Subthreshold and standby leakage powers at VDD=0.7V and 0.8V. It is found that the IP3 Cell has minimum subthreshold leakage current (at standby mode), i.e., 90%, 95%, 50%, and 51% as compared to the 6T, PP, P4, and P3 cells, respectively at no performance and stability loss with a small area penalty. The standby leakage power is better in P4, and P3 cells by 59%, and 23% to IP3 cell but at the cost of degraded cells’ data retentation and stability. The standby leakage power in IP3 is reduced by 36% and 52% in comparison with 6T and PP cell with improved cell stability and performance. The simulation has been carried out on tox= 2.4nm, Vthn= 0.22V, Vthp= 0.224V, VDD=0.8V, 0.7V, T= 270C.
Index Terms—SRAM, CMOS, low-power, gate leakage, leakage power, subthreshold current, oxide tunnelling.
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Cite: Manisha Pattanaik, Neeraj Kr. Shukla, and R. K. Singh, "Analysis and Simulation of Subthreshold Leakage Current Reduction in IP3 SRAM Bit-Cell at 45nm CMOS Technology for Multimedia Applications,"
International Journal of Computer Theory and Engineering vol. 3, no. 6, pp. 738-742, 2011.
