Abstract—Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage and reduced hardware cost with reduced design effort. The aim of this work is to contribute to reach these requirements for the design of self-checking adders/ALUs. In this paper, we present efficient self-checking implementations for adder schemes using the dual duplication code. Among the known self-checking adder designs, the dual duplicated scheme has the advantage to be totally self-checking for single faults. The drawback of this scheme is that it requires generally the maximum hardware overhead. In this work, we propose a low cost implementation for self-checking adder. The proposed design is based on a novel differential XOR gate implemented in CMOS pass transistor logic, and performed with only four transistors.
Index Terms—Totally self-checking circuits; self-checking adder; differential XOR; CMOS Logic Styles; CMOS pass transistor logic.
Belgacem Hamdi is with the Electronic & microelectronic‟s LAB, Monastir, Tunisia. PH.D. in Microelectronics from INP Grenoble (France). Assistant Professor at ISSAT Sousse, Tunisia. His main areas of interest are: IC design, Test, Built In self Test, DFT tools, self-checking and Fault tolerant systems. (E-mail: email@example.com)
Chiraz Khediri is with the Electronic & microelectronic‟s LAB, Monastir. Pursuing PH.D. in Electronic & microelectronic design at Tunis University, Tunisia.
Tourki Rached is the director of the Electronic & microelectronic's LAB, Monastir. Professor at FS Monastir university (Tunisia) (E-mail: firstname.lastname@example.org)
Cite: Hamdi Belgacem, Khedhiri Chiraz, and Tourki Rached, "Pass Transistor Based Self-Checking Full Adder," International Journal of Computer Theory and Engineering vol. 3, no. 5, pp. 608-616, 2011.