General Information
    • ISSN: 1793-8201 (Print), 2972-4511 (Online)
    • Abbreviated Title: Int. J. Comput. Theory Eng.
    • Frequency: Quarterly
    • DOI: 10.7763/IJCTE
    • Editor-in-Chief: Prof. Mehmet Sahinoglu
    • Associate Editor-in-Chief: Assoc. Prof. Alberto Arteta, Assoc. Prof. Engin Maşazade
    • Managing Editor: Ms. Mia Hu
    • Abstracting/Indexing: Scopus (Since 2022), INSPEC (IET), CNKI,  Google Scholar, EBSCO, etc.
    • Average Days from Submission to Acceptance: 192 days
    • E-mail: ijcte@iacsitp.com
    • Journal Metrics:

Editor-in-chief
Prof. Mehmet Sahinoglu
Computer Science Department, Troy University, USA
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.

IJCTE 2017Vol.9(5): 385-389 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2017.V9.1171

Hardware Implementation of Modified A5/1 Stream Cipher

Siti Yohana Akmal Mohd Fauzi, Marinah Othman, Farrah Masyitah Mohd Shuib, and Kamaruzzaman Seman

Abstract—Abstract— This paper describes the implementation of the modified cryptographic algorithm namely A5/1 stream cipher which is widely used in Global System for Mobile (GSM) communication. While there are numerous published work on the A5/1 stream, very few have implemented the modified design into hardware and none of them, to the best of the author’s knowledge, has clearly analyzed as to how the different characteristics of the conventional A5/1 stream cipher would affect performance at hardware level implementation. Two modified designs with different total bits and combinational functions are implemented into hardware by means of an Field Programmable Gate Array (FPGA) board and the throughput, area consumption, power consumption as well as the throughput-to-area ratio performance of the hardware are analysed and compared with that of the conventional design of the A5/1 stream cipher. While the algorithms in use have the same level of randomness, and hence strength in terms of security, at the hardware level, when total bits in use is increased, the total power consumed actually reduces. It is also observed that the use of the XOR logic has the better power consumption rate, compared to when a multiplexer is implemented as the combinational function.

Index Terms—Index Terms—A5/1 stream cipher, field programmable gate array, FPGA, throughput, cryptographic algorithm.

S. Y. A. M. Fauzi is with Faculty of Science and Technology, Universiti Sains Islam Malaysia, Bandar Baru Nilai, 71800 Nilai N. Sembilan, Malaysia (e-mail: sy.akmal91@ gmail.com). M. Othman, F. M. M. Shuib, and K. Seman are with the Faculty of Engineering and Built Environment, Universiti Sains Islam Malaysia, Bandar Baru Nilai, 71800 Nilai N. Sembilan, Malaysia (e-mail: marinah@usim.edu.my, farrah@usim.edu.my, drkzaman@usim.edu.my).

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Cite:Siti Yohana Akmal Mohd Fauzi, Marinah Othman, Farrah Masyitah Mohd Shuib, and Kamaruzzaman Seman, "Hardware Implementation of Modified A5/1 Stream Cipher," International Journal of Computer Theory and Engineering vol. 9, no.5, pp. 385-389 , 2017.


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