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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2017 Vol.9(5): 339-345 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2017.V9.1163

A SystemC Register Model for Multiple Levels of Abstraction Using Advanced Object-Oriented Design Patterns

Lillian Tadros
Abstract—Abstract—Available SystemC IP blocks are commonly modeled at either a cycle-accurate or a functional abstraction level. The large interval between these two choices, combined with non-trivial model replacement and integration effort, often leads to a prolonged use of the functional model, resulting in a verification gap once the model is eventually replaced with its cycle-accurate counterpart. A finer control of the granularity of both the adopted abstraction level and, even more important, the scope of the chosen abstraction, can thus enable localized, detailed analysis or verification with minimal impact on the simulation speed. This paper presents a model for processor registers in SystemC that makes use of several object-oriented design patterns in order to transparently change its behavior, starting from a functional model down to a cycle-accurate, pipelined version, while preserving the same interface. The register model has been integrated into a fork of the open-source processor generation tool TRAP-Gen, which generates SystemC processor models from high-level, Python-based descriptions.

Index Terms—Index Terms—Abstraction level, processor generation, registers, systemC.

L. Tadros is with the Technische Universität Dortmund, 44227 Dortmund, Germany (e-mail: lillian.tadros@tu-dortmund.de).

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Cite:Lillian Tadros , "A SystemC Register Model for Multiple Levels of Abstraction Using Advanced Object-Oriented Design Patterns," International Journal of Computer Theory and Engineering vol. 9, no. 5, pp. 339-345, 2017.

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