Abstract—Branch target buffer (BTB) is an important component for predicting branch target addresses to improve the performance of superscalar processor. However, BTB misprediction increases penalty by using deeper pipelines and larger windows in a current processor. Hence, increasing the accuracy of BTB prediction has become more important. This paper proposes a novel BTB that separates current BTB into conditional branch BTB (CBTB) and non-conditional branch BTB (NBTB). The CBTB uses the current BTB, and the NBTB is added on the current BTB. For optimization the separated BTB, we test NBTB by using two kinds of memory structures. One is static random access memory (SRAM) and the other is content addressable memory (CAM). For the replacement algorithms of CAM, we test a least recently used method and a rotation method. We equip our BTB on FPGA to measure the hardware size and use SimpleScalar to measure the performance. The experiment results show that proposed BTB improved IPC about 3.12% by adding an optimum of 128 entries to the current BTB with a CAM structure, and the optimal replacement algorithm is the rotation method.
Index Terms—Branch target buffer, superscalar processor, FPGA.
Authors are with the Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Shiga, Japan (e-mail: menglin@fc.ritsumei.ac.jp, {kumaki@fc, togura@se}.ritsumei.ac.jp).
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Cite:Lin Meng, Kosaku Fukuda, Takeshi Kumaki, and Takeshi Ogura, "An Optimal CAM-based Separated BTB for a Superscalar Processor," International Journal of Computer Theory and Engineering vol. 8, no. 2, pp. 122-128, 2016.
