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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2015 Vol.7(4): 311-315 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2015.V7.977

Design of Two-Rail Checker Using a New Parity Preserving Reversible Logic Gate

Trailokya Nath Sasamal, Ashutosh Kumar Singh, and Anand Mohan
Abstract—Reversible logic is one of the basis of future computing system that promises zero energy dissipation. It has applications in various fields such as Low power VLSI, Fault tolerant designs, quantum computing, nanotechnology, DNA computing, optical computing, cryptography and informatics. To make reversible logic circuits reliable, they must incorporate fault tolerance attribute. In this paper, we propose a new parity preserving reversible logic gate. We have proposed two optimized design of a self checking two rail checker circuit based on proposed parity preserving reversible logic gate in terms of number of gates and critical path delay. The proposed design achieves less critical delay and gates compared to the existing designs available in literature.

Index Terms—Critical delay, fault tolerant, paritypreserving reversible gates, two rail checker.

Trailokya Nath Sasamal and Anand Mohan are with the Electronics & Communication Department, NIT Kurukshetra-136119, India (e-mail: tnsasamal.ece@nitkkr.ac.in, profanandmohan@gmail.com). Ashutosh Kumar Singh is with the Department of Computer application, NIT Kurukshetra-136119, India (e-mail: ashutosh@nitkkr.ac.in).

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Cite:Trailokya Nath Sasamal, Ashutosh Kumar Singh, and Anand Mohan, "Design of Two-Rail Checker Using a New Parity Preserving Reversible Logic Gate," International Journal of Computer Theory and Engineering vol. 7, no. 4, pp. 311-315, 2015.

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