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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2015 Vol.7(3): 177-180 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2015.V7.952

Design of a Non-Overlapping Clock Generator for RFID Transponder EEPROM

Labonnah F. Rahman, Mamun B. I. Reaz, and Mohammad Marufuzzaman
Abstract—A non-overlapping clock (NOC) generator circuit is designed for the successful operation of high voltage generator (HVG) implementation in low-power applications like radio frequency identification (RFID) tag EEPROM. The NOC generator has been implemented in 0.18 μm CMOS process. The designed NOC can generate two stable anti-phase clock signals as output, which is used in charge pump (CP) circuit with low power dissipation. The NOC generator required lower power dissipation with 359.87 nW under power supply voltage (VDD) 1.8 V. Moreover, this designed NOC generator produced faster clock signals with 0.972 μS as the settling time.

Index Terms—NOC, HVG, RFID, CP, EEPROM.

Labonnah F. Rahman, Mamun B. I. Reaz, and Mohammad Marufuzzaman are with the Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment Universiti Kebangsaan Malaysia, 43600 UKM Bangi, Malaysia (e-mail: labonnah.deep@gmail.com, mamun.reaz@gmail.com, marufsust@gmail.com).

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Cite:Labonnah F. Rahman, Mamun B. I. Reaz, and Mohammad Marufuzzaman, "Design of a Non-Overlapping Clock Generator for RFID Transponder EEPROM," International Journal of Computer Theory and Engineering vol. 7, no. 3, pp. 177-180, 2015.

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