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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2013 Vol.5(5): 780-783 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2013.V5.795

Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Array

Esraa Zeki Mohammed and Haitham Kareem Ali
Abstract—In this paper a hardware implementation of an artificial neural network on Field Programmable Gate Arrays (FPGA) is presented. A digital system architecture is designed to realize a feed forward multilayer neural network. The designed architecture is described using Very High Speed Integrated Circuits Hardware Description Language (VHDL). The parallel structure of a neural network makes it potentially fast for the computation of certain tasks. The same feature makes a neural network well suited for implementation in VLSI technology. Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task.

Index Terms—Artificial neural network, hardware description language, field programmable gate arrays (FPGAs), sigmoid activation function.

Esraa Zeki Mohammed is with the State Company for Internet Services, Ministry of Communcation, Kirkuk, Iraq (e-mail: Isra_mohammed2@yahoo.com).
Haitham Kareem Ali is with the Communication Engineering Department, Sulaimani Technical College, Sulaimani, Iraq (e-mail: haitham_elect@yahoo.com).

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Cite:Esraa Zeki Mohammed and Haitham Kareem Ali, "Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Array," International Journal of Computer Theory and Engineering vol. 5, no. 5, pp. 780-783, 2013.

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