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General Information
Editor-in-chief
Prof. Wael Badawy
Department of Computing and Information Systems Umm Al Qura University, Canada
I'm happy to take on the position of editor in chief of IJCTE. We encourage authors to submit papers concerning any branch of computer theory and engineering.
IJCTE 2012 Vol.5(2): 346-350 ISSN: 1793-8201
DOI: 10.7763/IJCTE.2013.V5.707

Low Power FPGA Implementation of Digital FIR Filter Based on Low Power Multiplexer Base Shift/Add Multiplier

Bahram Rashidi, Farshad Mirzaei, Bahman Rashidi, and Majid Pourormazd
Abstract—In this paper, the authors present implementation of a low power and low area digital Finite Impulse Response (FIR) filter. The we method for reduce dynamic power consumption of a digital FIR filter is use of low power multiplexer based on shift/add multiplier without clock pulse and we applied it to fir filter until power consumption reduced thus reduce power consumption due to glitching is also reduced. The minimum power achieved is 56mw in fir filter based on shift/add multiplier in 100MHZ with 8bits inputs and 8bits coefficients. The proposed FIR filter was synthesized implemented using Xilinx ISE V7.1 and Virtex IV FPGA to target device xc4vlx200 also power is analized using Xilinx XPower analyzer.

Index Terms—Low Power, shift/add multiplier, barrel shifter.

Bahram Rashidi and Farshad Mirzaei are with the University of Tabriz, Iran (e-mail: bahram88@ms.tabrizu.ac.ir, Farshad.mirzaei@ymail.com).
Bahman Rashidi is with the Iran University of Science and Technology, Tehran, Iran (e-mail: b_rashidi@comp.iust.ac.ir).
Majid Pourormazd is with the University of Shahid chamran kerman , Iran (e-mail: Puorormazd@gmail.com).

[PDF]

Cite: Bahram Rashidi, Farshad Mirzaei, Bahman Rashidi, and Majid Pourormazd, "Low Power FPGA Implementation of Digital FIR Filter Based on Low Power Multiplexer Base Shift/Add Multiplier," International Journal of Computer Theory and Engineering vol. 5, no. 2, pp. 346-350, 2013.
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